디지털 패러다임 전환을 위한 터널링 기반 3진법 반도체 기술
Tunnelling-based ternary metal-oxide-semiconductor technology for digital paradigm shift
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김경록 UNIST The power density limits of complementary metal-oxide-semiconductor (CMOS) technology could be overcome by moving from a binary to a ternary logic system. Over the past several decades, however, ternary devices have typically been based on multi-threshold voltage schemes, which make the development of power-scalable and mass-producible ternary device platforms challenging. In this seminar, an overview for multi-valued logic (MVL) development history as well as CMOS technology will be firstly introduced. Then, a waferscale and energy-efficient ternary CMOS (T-CMOS) technology will be presented. Our approach is based on a single threshold voltage and relies on a third voltage state created using an off-state constant current that originates from quantum-mechanical band-to-band tunnelling (BTBT). This constant current can be scaled down to a sub-picoampere level under a low applied voltage of 0.5 V. Analysis of a ternary CMOS inverter illustrates the variation tolerance of the third intermediate output voltage state, and its symmetric in-out voltage-transfer characteristics allow integrated circuits with ternary logic and memory latch-cell functions to be demonstrated. We anticipate our findings to open a new digital paradigm of off-state working ternary devices and logic/memory building blocks for the realization of robustly power-scalable ternary-binary hybrid systems on semiconductor chips. |